1. Field of the Invention
This invention is related to the field of processors and, more specifically, to processors that execute predicated vector instructions.
2. Description of the Related Art
Vector processors exploit data-level parallelism (DLP) by performing the same operation on multiple vector elements in a source operand or operands. One issue that has prevented large-scale adoption of vector processors is the difficulty of vectorizing loops. To support loop vectorization, a vector instruction set has been proposed which includes predication on the vector elements. Thus, some vector elements may be operated upon while others are not (e.g. the results in inactive vector positions may be the previous value in that position or zero). Generally, a predicated vector instruction cannot be scheduled until its source operands and predicate operand are all known to be available either in the register file or forwarded to the instruction in the pipeline between scheduling and execution.